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ICSA Seminar talk by Prof Alberto Bardisa, University of Murcia, Spain

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Title: Non-Speculative Load-Load Reordering in TSO

  • Colloquium Series
When Oct 17, 2017
from 02:00 PM to 04:00 PM
Where IF 4.31/4.33
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WHEN: 17th Oct @ 2PM

WHERE: IF 4.31/4.33

SPEAKER: Prof Alberto Bardisa, University of Murcia, Spain

TITLE: Non-Speculative Load-Load Reordering in TSO

ABSTRACT: In current multicores loads can be speculatively reordered to improve performance. If a load-load reordering is seen by other cores, speculative loads must be squashed and re-executed. This talk shows that it is not necessary to squash and re-execute speculatively reordered loads when their reordering is seen to guarantee load-load order. Instead, the reordering can be hidden form other cores by the coherence protocol. The implication is that we can irrevocably bind speculative loads. This allows us to commit reordered loads out-of-order without having to wait (for the loads to become non-speculative) or without having to checkpoint committed state (and rollback if needed), just to ensure correctness in the rare case of some core seeing the reordering. By exposing a reordering to the coherence layer and by appropriately modifying a typical directory protocol we can successfully hide load-load reordering without perceptible performance cost and without deadlock. Our solution is cost-effective and increases the performance of out-of-order commit by a sizable margin, compared to the base case where memory operations are not allowed to commit if the consistency model could be violated.

BIO: Alberto Ros is Associate Professor at the University of Murcia, Spain. He received the PhD degree in computer science from the same university, in 2009, after being granted with a fellowship from the Spanish government to conduct the PhD studies. He hold postdoctoral positions at the Technical University of Valencia and at Uppsala University. He has co-authored more than 60 research papers in international journals and conferences. His research interests include cache coherence protocols, memory hierarchy designs, and memory consistency for multicore architectures.

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