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Architecture and Compiler Techniques to Improve Processor Energy Efficiency

Talk and presentation by Prof David Whalley- Florida State Univeristy

What
When Oct 10, 2011
from 03:30 PM to 04:30 PM
Where G.03
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Abstract:

A new generation of mobile applications is requiring reduced energy consumption without sacrificing application performance. We propose three separate techniques to address this challenge. The instruction register file (IRF) provides reduced energy consumption and decreased code size with little effect on execution time due to accessing frequently occurring instructions in registers. The lookahead instruction fetch engine (LIFE) provides lower energy consumption with no execution time penalty by making guarantees about instruction fetch behavior. The statically pipeline processor reduces energy consumption by providing simpler hardware that requires the control for each portion of the processor to be explicitly represented in each instruction. We will present an overview of these different techniques and evaluate their benefits.

 Bio:

David Whalley received his PhD in CS from the University of Virginia in 1990. He is currently the E.P. Miles professor and chair of the Computer Science Department at Florida State University. His research interests include low-level compiler optimizations, tools for supporting the development and maintenance of compilers, program performance evaluation tools, predicting execution time, computer architecture, and embedded systems. Some of the techniques that he developed for new compiler optimizations and diagnostic tools are currently being applied in industrial and academic compilers. His research is currently supported by the National Science Foundation. More information about his background and research can be found on his home page, http://www.cs.fsu.edu/~whalley.

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