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ICSA Colloquium Talk

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"De-synchronization : Synthesis of Asynchronous Circuits From Synchronous Specification" Christos Sotiriou, Foundation for Research and Technology Hellas (FORTH)

  • Colloquium Series
When Apr 04, 2008
from 02:00 PM to 03:00 PM
Where JCMB, ROOM 2511
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Christos Sotiriou
Foundation for Research and Technology Hellas (FORTH)

De-synchronization : Synthesis of Asynchronous Circuits From Synchronous Specification



Asynchronous circuits have always enjoyed significant focus from academia, but never managed to gain popularity with industry.

Some of the main hurdles include: the plethora of asynchronous design styles available, the non-industry standard specification languages used by researchers and academics, such as Petri-Net or CSP-based models, the incompatibility of these styles with industry-standard EDA design tools, the lack of mature tools which automatically synthesize high-level specifications to asynchronous circuits, and, last but not least, the steep learning curve that a digital designer must climb when faced with asynchronous design.

De-synchronization is an EDA methodology, whereby a synchronous circuit can be converted automatically to an asynchronous equivalent, without the need for the designer to possess any asynchronous design skills. In this way, de-synchronization enables, for the first time, the benefits of asynchronous circuits to be enjoyed and exploited, without the usual hurdles.

The talk will provide an overview of the fundamental concepts of De-synchronization, including the conversion process from a synchronous netlist to a de-synchronized equivalent, the correctness conditions for de-synchronized clocking and the design of handshake protocols for latch controllers.

De-synchronization is compatible with both ASIC and FPGA design flows. The elements of a complete, industrial tool compatible, de-synchronization EDA flow will be presented, which begins from a Verilog netlist and ends with an ASIC layout (or FPGA programming). The presented flow has been used to successfully implement and fabricate, in silicon, the multiplexed-clocking ASPIDA RISC microprocessor core, which is capable of operating both in synchronous and de-synchronized modes of operation.

Post-Silicon measurements of the ASPIDA chip in de-synchronization mode have demonstrated impressive voltage and power-scaling capabilities and adaptive frequency operation, an actual performance faster than that of the synchronous worst-case conditions, as predicted by EDA tools, and significantly reduced electromagnetic emissions compared to synchronous operation.


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