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ICSA Colloquium Talk

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"Programming multicores using the sequential paradigm" by Professor Chris Jesshope, Institute for Informatics, University of Amsterdam

  • Colloquium Series
When Dec 07, 2006
from 03:30 PM to 04:30 PM
Where JCMB, ROOM 2511
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Professor Chris Jesshope
Institute for Informatics, University of Amsterdam

Programming multicores using the sequential paradigm


This talk presents the thesis that the next generation of concurrent microprosessors will be highly-parallel,multicore devices and argues that there should be no deviation from the current methodology of sequential programming. The latter is based on a desire for deterministic and deadlock-free programs as well as a requirement for both source and binary compatibility where possible. However, how can this be achieved, with 25 years of research into parallel computers behind us and still no general solutions to automatic parallelisation. It will be argued that the problem is not in extracting concurrency, this has been demonstrated adequately by the dataflow community in the 1980s. Indeed one of the major problems in dataflow architectures is that of throttling of concurrency in order to avoid resource deadlock. If the problem is not finding concurrency, what then is the problem and how may it be solved. This talk argues that the only problem that must be overcome is that of scheduling concurrency and that static solutions adopted in the past are not sufficient in their power to solve it. Solutions must evolve from the dynamic management of concurrency as an integral part of the microprocessor's instruction set. The concept of Dynamic RISC (DRISC) or microthreading will be presented, which implements such instructions in its ISA. These allow the dynamic and determimistic distribution of concurrency between processors and the dynamic scheduling of individual instructions from large pools of threads associated with these processors. The latter requires fine-grain synchronisation to drive it. With these solutions in place, it will be demonstrated that binary compatibility can be achieved in chip multiprocessors, where a common binary will execute on an arbitrary number of processors up to some well defined limit, which is application specific. The talk will also discuss compilation strategies targeting the DRISC model by defining an intermediate language based on the instructions added to the processor's ISA. Dynamic solutions will be demonstrated that manage units of concurrency from single instructions up to complete sequential programs.


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