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ICSA COLLOQUIUM TALK

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Talk and presentation by Amitabha Roy, University of Cambridge. Title: Software Lock Elision for x86 Machine Code

What
  • Colloquium Series
When Apr 19, 2012
from 03:30 PM to 04:30 PM
Where IF- 4.31/4.33
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Abstract:

Software transactional memory has captured the imagination of the research community for much of the past decade but has thus far failed to find adoption by the software community. One of the reasons for this is the high development costs of integrating transactional memory with traditional software stacks: programming languages, compilers and debuggers. A possible solution to this problem is to transparently apply software transactional memory at the level of machine code.

This presentation describes the design of a runtime system that transparently elides legacy library locks in x86 machine code and executes the enclosed critical sections using transactions. There are two major stumbling blocks to this approach, solutions to which will be discussed in the talk.

The first is that runtime instrumentation of machine code using traditional dynamic binary rewriting is by itself too expensive. The second is that software transactional memory runtimes are usually built with relaxed language level memory consistency models in mind. The x86 memory consistency model (only recently formally defined) is much stricter, needing a whole new approach to building an STM for it.

Bio:

Amitabha Roy is a post-doctoral researcher in Computer Architecture at the University of Cambridge. His core interests are inter-disciplinary between systems and computer architecture. He is currently working on a variety of topics, primarily reducing coherence overheads in chip multiprocessors and techniques for accelarating the storage and processing of large graphs. Amitabha obtained his PhD from the University of Cambridge in 2011. His PhD thesis described the design and construction of a software transactional memory runtime system for x86 machine code. Prior to starting his PhD, he worked at Intel on performance and correctness issues for the memory hierarchies of a range of microprocessors then in development.

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