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Title: Energy Efficient Caches: Microarchitect's Point of View Presentation by Dr Nadhu Mutyam, Indian Institute of Technology Madras

  • Colloquium Series
When Jul 05, 2012
from 03:30 PM to 04:30 PM
Where 4.31/4.33
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Abstract: In order to tackle the memory wall problem, multi-level cache hierarchy is employed between the processor and main memory in modern computers. Caches occupy large portion of the chip area and consume significant percentage of the overall chip power budget. In this talk, we discuss sources of power consumption and possible avenues for power reduction in cache memories from microarchitects point of view.


Speaker's bio: Madhu Mutyam is an associate professor in the department of computer science and engineering, Indian Institute of Technology Madras. His research interests include multicore architectures and VLSI CAD. He is a senior member of ACM and IEEE.


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