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Past Events

List of events which have passed.

Lab Lunch by Kousha Etessami

The complexity of computing a (quasi-)perfect equilibrium for an n-player extensive form game of perfect recall.

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LFCS Seminar: Conor McBride

Do Be Do Be Do (Smooth Effect and Value Polymorphism with Frank)

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LFCS Seminar: Christian Urban

Formalising Regular Language Theory with Regular Expressions

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Lab Lunch by Stuart Anderson

Balancing foundational and translational research in School of Informatics

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LFCS Seminar: Julian Gutierrez

Determinacy for concurrent games on event structures

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LFCS Seminar: Paolo Zuliani

Verification of Stochastic Systems by Statistical Model Checking

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Lab Lunch by Perdita Stevens

What happens at an EPSRC prioritisation panel?

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Lab Lunch by Kyriakos Kalorkoti

Making Photographs in the Highlands in the Shadow of History

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Lab Lunch by Jiansen He

Having Cloud in Hand: Google vs Amazon

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Lab Lunch: Prof Andrew D. Gordon

Title: Experience with Verifying Cryptographic Software in C

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Lab Lunch by Karoliina Lehtinen

Eliminating complexity in modal mu calculus & a brief survey of folk dancing in Edinburgh and elsewhere.

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LFCS Seminar: Jean-Raymond Abrial

Formalizing Hybrid Systems with Event-B

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Vijayanand Nagarajan: Towards Semantics-directed Hardware Memory Consistency

The memory consistency model which mandates what value a memory read can return, is at the heart of shared memory concurrency. With regard to memory consistency models, an inherent trade-off between programmability and performance is presumed. For instance, it is thought that implementing sequential consistency (SC) would be too expensive as it is presumed that it would preclude hardware optimisations such as write-buffering. In this talk, we show that prior hardware SC implementations are overly restrictive in that they do not exploit most of the concurrency opportunities allowed by SC. We proceed to show how SC can be implemented efficiently while retaining hardware optimisations such as write-buffering. We conclude by arguing for semantics-directed hardware design for realising programmable, yet efficient shared memory consistency models.

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