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Vijayanand Nagarajan: Towards Semantics-directed Hardware Memory Consistency

The memory consistency model which mandates what value a memory read can return, is at the heart of shared memory concurrency. With regard to memory consistency models, an inherent trade-off between programmability and performance is presumed. For instance, it is thought that implementing sequential consistency (SC) would be too expensive as it is presumed that it would preclude hardware optimisations such as write-buffering. In this talk, we show that prior hardware SC implementations are overly restrictive in that they do not exploit most of the concurrency opportunities allowed by SC. We proceed to show how SC can be implemented efficiently while retaining hardware optimisations such as write-buffering. We conclude by arguing for semantics-directed hardware design for realising programmable, yet efficient shared memory consistency models.

What
When May 01, 2012
from 01:00 PM to 02:00 PM
Where Mini Forum 2
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